1. Field of the Invention
The present invention relates generally to voltage generating circuits for a semiconductor device, and more particularly, to an improvement of a circuit for generating a voltage to be applied to a predetermined part of a semiconductor device.
2. Description of the Background Art
In a semiconductor device such as a dynamic RAM, a voltage generating circuit is provided for generating a voltage to be applied to cell plates and bit lines.
FIG. 1 is a circuit diagram showing a voltage generating circuit for such a conventional semiconductor memory device, which is shown in U.S. Pat. No. 4,788,455. In the drawing, the voltage generating circuit comprises n-type field effect transistors 1-3, p-type field effect transistors 4-6, and resistors 7-10. Two serial connection circuits 31 and 32 are interposed in parallel between a power supply line 20 and a ground. The first serial connection circuit 31 comprises the resistor 7, the n-type field effect transistors (hereinafter referred to as n-FET) 1 and 2 and the resistor 8 connected in series. The resistor 7 has one end connected to the power supply line 20, and the other end connected to a drain electrode and a gate electrode of the n-FET 1. A source electrode of the n-FET 1 is connected to a drain electrode and a gate electrode of the n-FET 2. A source electrode of the n-FET 2 is connected to one end of the resistor 8. The other end of the resistor 8 is connected to the ground. On the other hand, the second serial connection circuit 32 comprises the resistor 9, the p-type field effect transistors (hereinafter, referred to as p-FET) 4 and 5, and the resistor 10 connected in series. The resistor 9 has one end connected to the power supply line 20, and the other end connected to a source electrode of the p-FET 4. A drain electrode of the p-FET 4 is connected to its gate electrode and a source electrode of the p-FET 5. A drain electrode of the p-FET 5 is connected to its gate electrode and one end of the resistor 10. The other end of the resistor 10 is connected to the ground. The n-FET 3 and p-FET 6 are connected in series to be interposed between the power supply line 20 and the ground. More specifically, the n-FET 3 has its drain electrode connected to the power supply line 20, and its source electrode connected to a source electrode of the n-FET 6. A drain electrode of the p-FET 6 is connected to the ground, while a gate electrode of the n-FET 3 is connected to the drain electrode of the n-FET 1, and a gate electrode of the p-FET 6 is connected to the drain electrode of the p-FET 5. An output V.sub.out is taken from a node between the source electrode of the n-FET 3 and the source electrode of the p-FET 6.
Now, operation of the voltage generating circuit shown in FIG. 1 will be described. When a power supply is turned on, a power supply voltage V.sub.CC is applied to the power supply line 20, so that n-FETs 1 and 2 are rendered conductive, and the p-FETs 4 and 5 also rendered conductive. Now, assuming that a resistance value R7 of the resistor 7 and a resistance value R8 of the resistor 8 are equal (R7=R8), a potential at a node between the drain electrode of the n-FET 1 and the resistor 7, that is, a gate potential of the n-FET 3 becomes as represented by the following equation, EQU (V.sub.CC /2)+V.sub.thn
while a potential at a node between the drain electrode of the p-FET 5 and the resistor 10, that is, a gate potential of the p-FET 6 is represented by the following equation, EQU (V.sub.CC /2)-V.sub.thp
Accordingly, when the output voltage V.sub.OUT becomes larger than V.sub.CC /2, the p-FET 6 is rendered conductive so that the output voltage V.sub.OUT drops. On the other hand, when the output voltage V.sub.OUT becomes smaller than V.sub.CC /2, the n-FET 3 is rendered conductive, so that the output voltage V.sub.OUT rises. Accordingly, the output voltage V.sub.OUT is always held at V.sub.CC /2.
More specifically, the voltage generating circuit of FIG. 1 is a voltage generating circuit for stably generating a voltage V.sub.CC /2 which is half of the power supply voltage.
Since a conventional voltage generating circuit is constructed as the above, currents always flow through the first serial connection circuit 31 and the second serial connection circuit 32. Therefore, resistance values of the resistors 7-10 should be made larger in order to reduce power consumption. However, because the resistors 7-10 are formed by diffusion resistance in a semiconductor substrate, the area of the resistors is increased in proportion to the resistance values. As a result, a circuit area of a voltage generating circuit became larger. The resistors 7 and 8, and 9 and 10 form voltage dividing circuits for generating each gate potential of the n-FET 3 and p-FET 6, respectively. Therefore, if resistance values become larger, fluctuation of the power supply voltage V.sub.CC causes accuracy of detection of a reference voltage to be generated in each voltage dividing circuit to be rendered, so that the output voltage V.sub.OUT could not be held at V.sub.CC /2.